Power supply monitoring integrated circuit device for individually monitoring voltages of cells

ABSTRACT

A power supply monitoring integrated circuit device for individually detecting the voltages of a plurality of lithium-ion cells connected in series has a plurality of comparators for comparing the voltages obtained by dividing the voltages of the individual cells with a predetermined voltage. The power supply monitoring integrated circuit device also has terminals for feeding electric power from the individual cells through resistors to the inputs of the individual comparators and terminals for supplying electric power from the individual cells to the individual comparators, and, in accordance with the results of comparison by the individual comparators, controls charging or discharging of the cells.

TECHNICAL FIELD

The present invention relates to an integrated circuit device formonitoring power supply (hereafter a “power supply monitoring IC”) thatis used to prevent a lithium-ion cell or the like from being broughtinto an overdischarged or overcharged state.

BACKGROUND ART

A conventional power supply monitoring IC will be described below withreference to FIG. 3. In FIG. 3, reference numeral 72 represents a powersupply apparatus (hereafter a “battery pack”) having lithium-ion cells 2and 3 and a power supply monitoring IC 73. When the cells 2 and 3 arecharged, terminals 11 and 12 are connected to a power source forcharging (not shown), and, when the battery pack 72 is in use, a load(not shown) is connected to the terminals 11 and 12.

In normal use, the lithium-ion cells 2 and 3 each have a voltage from2.3 V to 4.2 V. Accordingly, for example, the power supply monitoring IC73, when the voltage becomes higher than 4.3 V, inhibits charging toprevent overcharging, and, when the voltage becomes lower than 2.2 V,inhibits discharging to prevent overdischarging.

Now, the portion of this conventional power supply monitoring IC 73 thatdetects overdischarging will be described. The portion that detectsovercharging will not be described; nor is it shown in FIG. 3. Of thetwo lithium-ion cells 2 and 3, the cell 2 is placed on the higherpotential side. The higher potential end of the cell 2 is connected tothe positive terminal 11 of the battery pack 72. On the other hand, thelower potential end of the cell 3 is connected to the drain of ann-channel MOSFET (metal-oxide semiconductor field-effect transistor) 8.The source of the MOSFET 8 is connected to the negative terminal 12. Thegate of the MOSFET 8 is connected to a terminal T1 of the power supplymonitoring IC 73, so that the MOSFET 8 is turned on and off by the powersupply monitoring IC 73.

The higher potential end of the cell 2 is connected through a protectionresistor R5 to a terminal U1 of the power supply monitoring IC 73. Thenode between the cells 2 and 3 is connected through a protectionresistor R6 to a terminal U2. The lower potential end of the cell 3 isconnected to a terminal GND of the power supply monitoring IC 73.

During discharging or charging, the power supply monitoring IC 73 turnson the MOSFET 8 so that electric power is supplied from the cells 2 and3 to an electronic appliance or the like connected to the terminals 11and 12. On the other hand, during charging, a direct-current voltage isapplied from a direct-current power source or the like to the terminals11 and 12, and thereby the cells 2 and 3 are charged.

The protection resistors R5 and R6 have a resistance of about 1kΩ andserve to prevent infiltration of noise into the power supply monitoringIC 73 which may result in electrostatic destruction of the power supplymonitoring IC 73. Moreover, the protection resistors R5 and R6 alsoserve to protect the cells 2 and 3 from destruction by preventing thecells 2 and 3 from being short-circuited even when the terminal U1 or U2is short-circuited to the terminal GND.

Between the terminals U1 and U2, resistors R1 and R2 are connected inseries. The voltage at the node between the resistors R1 and R2 is fedto the non-inverting input terminal (+) of a comparator 4. To theinverting input terminal (−) of the comparator 4, a voltage higher thanthe voltage at the terminal U2 by a reference voltage V1 is fed. Thecomparator 4 receives electric power via the terminal U1. Thus, thecomparator 4 compares the voltage of the cell 2 with a predeterminedoverdischarge voltage. The overdischarge voltage is set, for example, at2.2 V. The comparator 4 outputs a low level if the voltage of the cell 2is lower than the overdischarge voltage, and outputs a high level if thevoltage of the cell 2 is higher than the overdischarge voltage.

Between the terminals U2 and GND, resistors R3 and R4 are connected inseries. The voltage at the node between the resistors R3 and R4 is fedto the non-inverting input terminal (+) of a comparator 5. The terminalGND is grounded so as to be at the ground level. To the inverting inputterminal (−) of the comparator 5, a voltage higher than the ground levelby a reference voltage V2 is fed. The resistances of the resistors R1and R3 are equal, and the resistances of the resistors R2 and R4 areequal. The reference voltages V1 and V2 are equal. Thus, the voltages ofthe cells 2 and 3 are checked against the same overdischarge voltage.

The outputs of the comparators 4 and 5 are fed to an AND circuit 6.Thus, when the voltages of both of the cells 2 and 3 are higher than theoverdischarge voltage, the AND circuit 6 outputs a high level. Bycontrast, when the voltage of at least one of the cells 2 and 3 is lowerthan the overdischarge voltage, the AND circuit 6 outputs a low level.In this way, when the voltages of both of the cells 2 and 3 are higherthan the overdischarge voltage, the AND circuit 6 outputs a high levelthat is used as a discharge enable signal SD. The discharge enablesignal SD is fed to a discharge control circuit 7.

While the discharge control circuit 7 is receiving the discharge enablesignal SD, the discharge control circuit 7 applies a signal to the gateof the MOSFET 8, which is connected to the terminal T1, to turn on theMOSFET 8. By contrast, while the discharge control circuit 7 is notreceiving the discharge enable signal SD, it keeps the MOSFET 8 off. Asa result, the cells 2 and 3 are disconnected from the load, and therebydischarging is stopped. In this way, the cells 2 and 3 are preventedfrom being brought into an overdischarged state.

However, in this conventional power supply monitoring IC 73, voltagedrops are caused across external impedance, such as the protectionresistors R5 and R6 and wiring resistances, by the current flowingtherethrough, and this causes an error in the detected voltages of thecells 2 and 3. Thus, variations in the current flowing into the powersupply monitoring IC 73 and variations in external impedance degradedetection accuracy. For example, in the case of the comparator 5, whichreceives electric power through the resistor R6, a variation in thevoltage resulting from electric power being supplied appears at thevoltage division point, and such a variation appearing at the voltagedivision point as a result of electric power being supplied is difficultto correct. Now suppose that the power supply monitoring IC 73 monitorsthe overdischarge voltage with accuracy of about 50 mV, that the currentflowing through the resistor R6 via the terminal U2 as the operationcurrent of the comparator 5 is tens of microamperes, and that theresistor R6 has a resistance of 1 kΩ, then a voltage drop of tens ofmicrovolts occurs. In this way, variations in the resistances of theprotection resistors, in wiring resistances, and in the operationcurrent cause an error in detection accuracy as large as such a voltagedrop, and thereby degrade detection accuracy. Furthermore, the currentflowing through the resistors R1 and R2 in the upper stage flows alsothrough the resistors R3 and R4, and this also causes an error in thevoltage at the voltage division point with respect to the voltage thatshould be present there.

Moreover, in case the resistor R6 is disconnected from the terminal U2by an accidental cause such as improper soldering or a mechanical shock,the resistors R1 to R4 are left connected simply in series, andtherefore the comparators 4 and 5 erroneously recognize the averagevoltage of the cells 2 and 3 as the voltages of the cells 2 and 3,respectively. For example, if such a disconnection occurs at theterminal U2 when the voltage of one of the cells 2 and 3 equals theoverdischarge voltage 2.2 V and the voltage of the other equals 3.4 V,the comparators 4 and 5 both recognize the average voltage(2.2+3.4)/2=2.8 V as the voltages of the individual cells 2 and 3 andcompare this voltage with the overdischarge voltage 2.2 V. As a result,the AND circuit 6 outputs the discharge enable signal SD to continuedischarging, bringing the cells into an overdischarged state.

DISCLOSURE OF THE INVENTION

An object of the present invention is to provide a power supplymonitoring IC that offers more secure protection of lithium-ion cellsand the like by detecting voltages with higher accuracy and by makingcorrect judgments even when a disconnection occurs at an intermediateterminal like U2.

According to the present invention, a power supply monitoring integratedcircuit device for individually monitoring the voltages of a pluralityof cells connected in series to control charging or dischargingoperation of the cells is provided with a plurality of pairs of inputterminals provided one pair for each of the cells for receiving thevoltages of the cells; a plurality of voltage dividing means fordividing the voltages of the cells received via the input terminals; aplurality of comparators for comparing output voltages of the voltagedividing means with a predetermined voltage; a plurality of electricpower input terminals for receiving electric power fed through resistorsfrom higher-potential ends of the cells to operate the comparators; acontrol means connected to the comparators so as to generate a stopsignal for stopping the charging or discharging operation when thevoltage of at least one of the cells exceeds the predetermined voltage;and an output terminal connected to the control means for outputting thestop signal.

According to this circuit configuration, while the voltages of the cellsconnected to the power supply monitoring IC are being monitored, even ifa disconnection due to improper soldering occurs at a terminal that isconnected to a node between the cells, the power supply monitoring IC,having separate terminals for receiving the voltages of the individualcells, never makes a wrong judgment as does the conventional powersupply monitoring IC described earlier. Thus, it is possible to securelyprotect the cells. Moreover, for every node between the cells, aterminal for feeding a voltage to the corresponding comparator and aterminal for supplying electric power thereto are provided separately,and thereby the current flowing at the terminal for feeding the voltageis reduced accordingly. This makes it possible to reduce voltage dropsand thereby increase detection accuracy.

Moreover, by giving a high impedance to such terminals for feeding avoltage, it is possible to greatly reduce the current flowing at thoseterminals, and thereby reduce the voltage drops across externalimpedance. This helps reduce the influence of variations in externalimpedance and in the current and thereby increase detection accuracy.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of the power supply monitoring IC of a firstembodiment of the present invention, FIG. 2 is a block diagram of thepower supply monitoring IC of a second embodiment of the presentinvention, and FIG. 3 is a block diagram of a battery pack employing aconventional power supply monitoring IC.

BEST MODE FOR CARRYING OUT THE INVENTION

<First Embodiment>

A first embodiment of the present invention will be described withreference to FIG. 1. FIG. 1 is a block diagram of a battery pack 10employing a power supply monitoring IC 1 that monitors overdischargingof cells 2 and 3. Such elements as are found also in the battery pack 72employing the conventional power supply monitoring IC 73 (see FIG. 3)described earlier are identified with the same reference numerals andsymbols, and overlapping descriptions will not be repeated.

In the power supply monitoring IC 1, an electric power supply terminalUC1 and a voltage detection terminal U1 are provided separately. Theelectric power supply terminal UC1 is connected through a protectionresistor R7 to the higher potential end of the lithium-ion cell 2. Thevoltage detection terminal U1 is connected through a protection resistorR8 to the higher potential end of the lithium-ion cell 2. The higherpotential end of the cell 2 is connected to a positive terminal 11.

Similarly, as an intermediate terminal, an electric power supplyterminal UC2 and a voltage detection terininal U2 are providedseparately. The electric power supply terminal UC2 is connected througha protection resistor R9 to the node between the lithium-ion cells 2 and3. The voltage detection terminal U2 is connected through a protectionresistor R10 to the node between the lithium-ion cells 2 and 3. Notethat an intermediate terminal refers to a terminal that is connected toa node between cells, like UC2 and U2 connected to the node between thecells 2 and 3. The lower potential end of the cells 2 and 3 is connectedto the drain of a MOSFET 8 and to a terminal GND of the power supplymonitoring IC 1. The terminal GND is grounded so as to be at the groundlevel. The source of the MOSFET 8 is connected to a negative terminal12.

The protection resistors R7 to R10 have a resistance of, for example,about 1 kΩ. Between the terminals U1 and UC2, resistors R1 and R2 areconnected in series. For example, the resistor R1 has a resistance of 3kΩ, and the resistor R2 as a resistance of 1 kΩ.

The voltage at the node between the resistors R1 and R2 is fed to thenon-inverting input terminal (+) of a comparator 4. To the invertinginput terminal (−) of the comparator 4, a voltage higher than thevoltage at the terminal UC2 by a reference voltage V1 is fed. Thecomparator 4 receives electric power via the terminal UC1. Thecomparator 4 compares the voltage of the cell 2 with a predeterminedoverdischarge voltage that is applied to its inverting input terminal(−). Thus, the comparator 4 outputs a low level when the voltage of thecell 2 is lower than the overdischarge voltage, and outputs a high levelwhen the voltage of the cell 2 is higher than the overdischarge voltage.

The current that flows from the electric power supply terminal UC1 intothe comparator 4 is tens of microamperes. The current that flows fromthe voltage detection terminal U1 into the resistors R1 and R2 is assmall as several microamperes owing to a high impedance. Thus, if theresistors R8 and R10 have a resistance of 1 kΩ, the voltage drops acrossthe resistors R8 and R10 are about 1 mV. In this way, even if wiringresistances are taken into consideration, voltage drops across externalimpedance are kept smaller on the side of the voltage detectionterminals U1 and U2. This helps eliminate the influence of thecomparators that may degrade voltage detection accuracy, and thus it ispossible to increase voltage detection accuracy.

Between the terminals U2 and GND, resistors R3 and R4 are connected inseries. The voltage at the node between the resistors R3 and R4 is fedto the non-inverting input terminal (+) of a comparator 5. To theinverting input terminal (−) of the comparator 5, a voltage higher thanthe ground level by a reference voltage V2 is fed.

The resistances of the resistors R1 and R3 are equal, and theresistances of the resistors R2 ad R4 are equal. The reference voltagesV1 and V2 are equal. Thus, the voltages of the cells 2 and 3 are checkedagainst the same overdischarge voltage. The outputs of the comparators 4and 5 are fed to an AND circuit 6. Thus, when the voltages of both ofthe cells 2 and 3 are higher than the overdischarge voltage, the ANDcircuit 6 outputs a high level that is used as a discharge enable signalSD.

When the discharge enable signal SD is fed to a discharge controlcircuit 7, the discharge control circuit 7 applies a voltage to the gateof the MOSFET 8, which is connected to the terminal T1, to turn on theMOSFET 8. By contrast, when the voltage of at least one of the cells 2and 3 becomes lower than the overdischarge voltage, the dischargecontrol circuit 7 turns off the MOSFET 8.

In this way, by providing the electric power supply terminals UC1 andUC2 and the voltage detection terminals U1 and U2 separately, it ispossible to reduce the current flowing at the voltage detectionterminals U1 and U2 to almost zero. This makes it possible to minimizethe error in the detected electric power due to voltage drops acrossexternal impedance, such as the protection resistors R8 and R10 andwiring resistances, and thereby increase voltage detection accuracy.

When, for example, the resistor R10 is disconnected from theintermediate terminal U2 because of improper soldering or the like, theground level is fed to the non-inverting input terminal (+) of thecomparator 5. Thus, the comparator 5 behaves as if the voltage of thecell 3 were 0 V, and therefore outputs a low level. Accordingly, the ANDcircuit 6 stops outputting the discharge enable signal SD. As a result,the MOSFET 8 is turned off, and thus the discharging of the cells 2 and3 is inhibited. The result of comparison by the comparator 4 is notaffected.

Similarly, when the resistor R9 is disconnected from the electric powersupply terminal UC2, no electric power is supplied to the comparator 5.Thus, the comparator 5 stops operating. Accordingly, the AND circuit 6does not output the discharge enable signal SD. As a result, the MOSFET8 is turned off, and thus the discharging of the cells 2 and 3 isinhibited. In this way, even if a disconnection occurs at theintermediate terminal UC2 or U2, it is possible to make a correctjudgment and thereby prevent the cells 2 and 3 from being brought intoan overdischarged state, with their characteristics degraded. This makesit possible to securely protect the cells.

The terminals UC1 and U1 may be provided as a single terminal. In thatcase, the resistors Ri and R2 are connected in series between thisterminal and the terminal UC2, and electric power is supplied to thecomparator 4 via this terminal. Even in this case, when a disconnectionoccurs at the intermediate terminal UC2 or U2, the MOSFET 8 is turnedoff in the same manner as described above. The MOSFET 8 may be replacedwith a switching device of any other type. The overdischarge voltagedoes not necessarily have to be 2.2 V, but may be set at any othervoltage.

<Second Embodiment>

A second embodiment of the present invention will be described withreference to FIG. 2. FIG. 2 is a block diagram of a battery pack 70employing a power supply monitoring IC 80 that monitors overdischargingand overcharging. The power supply monitoring IC 80 monitors fourlithium-ion cells 21 to 24 to prevent them from being brought into anoverdischarged or overcharged state.

The cells 21 to 24 are connected in series in this order from thehighest potential end. The higher potential end of the cell 21 isconnected to a positive terminal 60 of the battery pack 70, and thelower potential end of the cell 24 is connected to the drain of ann-channel MOSFET 55 provided for discharge control. The source of theMOSFET 55 is connected to the drain of an n-channel MOSFET 56 providedfor charge control. The gate of the MOSFET 55 is connected to a terminalT1 of the power supply monitoring IC 80.

The source of the MOSFET 56 is connected to a negative terminal 61, thegate of the MOSFET 56 is connected to a terminal T2 of the power supplymonitoring IC 80. As will be described later, the MOSFETs 55 and 56 areturned on and off by the power supply monitoring IC 80. Duringdischarging, electric power is supplied to a personal computer 71 thatis connected to terminals 60 and 61.

An electric power supply terminal UC1 is connected through a protectionresistor R40 to the higher potential end of the cell. A voltagedetection terminal U1 is connected through a protection resistor R41 tothe higher potential end of the cell 21. Intermediate terminals areprovided as follows. An electric power supply terminal UC2 is connectedthrough a protection resistor R42 to the node between the cells 21 and22. A voltage detection terminal U2 is connected through a protectionresistor R43 to the node between the cells 21 and 22.

An electric power supply terminal UC3 is connected through a protectionresistor R44 to the node between the cells 22 and 23. A voltagedetection terminal U3 is connected through a protection resistor R45 tothe node between the cells 22 and 23. An electric power supply terminalUC4 is connected through a protection resistor R46 to the node betweenthe cells 23 and 24. A voltage detection terminal U4 is connectedthrough a protection resistor R47 to the node between the cells 23 and24. The protection resistors R40 to R47 have a resistance of, forexample, 1 kΩ.

Via the electric power supply terminals UC1 to UC4, electric power issupplied to comparators 30 to 33, and to comparators 40 to 43,respectively. Between the terminals U1 and UC2, resistors R20 and R21are connected in series. The voltage at the node between the resistorsR20 and R21 is fed to the non-inverting input terminal (+) of thecomparator 30. To the inverting input terminal (−) of the comparator 30,a voltage higher than the voltage at the electric power supply terminalUC2 by a reference voltage Va is fed.

Similarly, between the voltage detection terminal U2 and the electricpower supply terminal UC3, resistors R22 and R23 are connected inseries. The voltage at the node between the resistors R22 and R23 is fedto the non-inverting input terminal (+) of the comparator 31. To theinverting input terminal (−) of the comparator 31, a voltage higher thanthe voltage at the electric power supply terminal UC3 by a referencevoltage Vb is fed.

Similarly, between the terminals U3 and UC4, resistors R24 and R25 areconnected in series. The voltage at the node between the resistors R24and R25 is fed to the non-inverting input terminal (+) of the comparator32. To the inverting input terminal (−) of the comparator 32, a voltagehigher than the voltage at the electric power supply terminal UC4 by areference voltage Vc is fed.

Similarly, between the terminals U4 and GND, resistors R26 and R27 areconnected in series. The voltage at the node between the resistors R26and R27 is fed to the non-inverting input terminal (+) of the comparator33. To the inverting input terminal (−) of the comparator 33, a voltagehigher than the ground level by a reference voltage Vd is fed.

The resistances of the resistors R20, R22, R24, and R26 are equal, forexample 3 MΩ. The resistances of the resistors R21, R23, R25, and R27are equal, for example 1 MΩ. The reference voltages Va to Vd are equal.The comparators 30 to 33 compare the voltages of the individual cells 21to 24 with an overdischarge voltage. The overdischarge voltage is set,for example, at 2.2 V.

The outputs of the comparators 30 to 33 are fed to an AND circuit 50.Thus, when the voltages of all of the cells 21 to 24 are higher than theoverdischarge voltage, the AND circuit 50 outputs a discharge enablesignal SD. The output of the AND circuit 50 is fed to a dischargecontrol circuit 51. When the discharge enable signal SD is fed to thedischarge control circuit 51, the discharge control circuit 51 applies avoltage to the gate of the MOSFET 55, which is connected to the terminalT1, to turn on the MOSFET 55.

By contrast, when the voltage of at least one of the cells 21 to 24becomes lower than the overdischarge voltage, the AND circuit 50 stopsoutputting the discharge enable signal SD. Thus, the discharge controlcircuit 51 turns off the MOSFET 55. In this way, during discharging, thepower supply monitoring IC 80 monitors the cells 21 to 24 to preventthem from being brought into an overdischarged state.

On the other hand, during charging, the power supply monitoring IC 80monitors the cells 21 to 24 to prevent them from being brought into anovercharged state. Between the terminals U1 and UC, resistors R30 andR31 are connected in series. The voltage at the node between theresistors R30 and R31 is fed to the non-inverting input terminal (+) ofthe comparator 40. To the inverting input terminal (−) of the comparator40, a voltage higher than the voltage at the terminal UC2 by a referencevoltage Ve is fed. Thus, the comparator 40 outputs a high level when thevoltage of the cell 21 is higher than a predetermined overchargevoltage, and outputs a low level when the voltage of the cell 21 islower than the overcharge voltage. The overcharge voltage is set, forexample, at 4.3 V.

Similarly, between the terminal U2 and UC3, resistors R32 and R33 areconnected in series. The voltage at the node between the resistors R32and R33 is fed to the non-inverting input terminal (+) of the comparator41. To the inverting input terminal (−) of the comparator 41, a voltagehigher than the voltage at the terminal UC3 by a reference voltage Vf isfed.

Similarly, between the terminals U3 and UC4, resistors R34 and R35 areconnected in series. The voltage at the node between the resistors R34and R35 is fed to the non-inverting input terminal (+) of the comparator42. To the inverting input terminal (−) of the comparator 42, a voltagehigher than the voltage at the terminal UC4 by a reference voltage Vg isfed.

Similarly, between the terminals U4 and GND, resistors R36 and R37 areconnected in series. The voltage at the node between the resistors R36and R37 is fed to the non-inverting input terminal (+) of the comparator43. To the inverting input terminal (−) of the comparator 43, a voltagehigher than the ground level by a reference voltage Vh is fed.

The outputs of the comparators 40 to 43 are fed to an OR circuit 52.Thus, when the voltage of at least one of the cells 21 to 24 is higherthan the overcharge voltage, the OR circuit 52 outputs a high level. Bycontrast, when the voltages of all of the cells 21 to 24 are lower thanthe overcharge voltage, the OR circuit 52 outputs a low level. In thisway, the OR circuit 52 outputs a charge inhibition signal SC. The outputof the OR circuit 52 is fed to a charge control circuit 53.

When the charge control circuit 53 is not receiving a high level as thecharge inhibition signal SC, it applies a voltage to the gate of theMOSFET 56, which is connected to the terminal T2, to turn on the MOSFET56. By contrast, when the charge control circuit 53 receives a low levelas the charge inhibition signal SC, it turns off the MOSFET 56. In thisway, while the cells 21 to 24 are being charged via the terminals 60 and61, the voltages of the individual cells 21 to 24 are monitored to checkwhether they are higher than the overcharge voltage or not so that, ifthe voltage of any of the cells 21 to 24 is higher than the overchargevoltage, the MOSFET 56 is turned off to inhibit charging.

By the use of the power supply monitoring IC 80 of this embodiment, itis possible to monitor four lithium-ion cells 21 to 24 connected inseries to prevent them from being brought into an overdischarged orovercharged state. Since the resistors R20 to R27 ensure a highimpedance, almost no current flows at the voltage detection terminals U1to U4. This helps minimize the voltage drops across the protectionresistors R41, R43, R45, and R45 and across wiring resistances, andthereby minimize detection errors.

Moreover, for the same reasons as given previously in the descriptionsof the first embodiment, even if a disconnection occurs because ofimproper soldering at the intermediate terminals U2 to U4 and UC2 toUC4, the disconnection does not cause a wrong judgment. Thus, even insuch a case, the power supply monitoring IC 80 turns off the MOSFET 55and thereby prevents the cells 21 to 24 from being brought into anoverdischarged state. Similarly, the comparators 40 to 43 for detectingan overcharge voltage do not make a wrong judgment.

When the lithium-ion cells 21 to 24 are subjected to overcurrent, thereis a risk of smoking or the like. For this reason, it is also possibleto provide the power supply monitoring IC 80 with a function forpreventing overcurrent. For example, by exploiting the on-stateresistance of the MOSFET 55 or the like, the current flowingtherethrough is converted into a voltage so that, when the detectedvoltage indicates overcurrent, the MOSFET 55 is turned off.

As shown in FIG. 2, the power supply monitoring IC 80 employs the samecircuit configuration for each of the cells 21 to 24, and therefore canbe designed to monitor any number, like 2, 3, . . . , of cells. Forexample, a power supply monitoring IC designed to monitor two or threecells can be used in a portable telephone, portable video recorder, orthe like; a power supply monitoring IC designed to monitor three or fourcells can be used, as shown in FIG. 2, in a personal computer 71, or thelike. The battery pack 70 of this embodiment can be used not only in apersonal computer 71, but also in an appliance of any other kind.

The MOSFETs 55 and 56 may be inserted anywhere as long as they can, whenturned off, inhibit the discharging or charging of the cells 21 to 24.As described previously, the terminals UC1 and U1 may be provided as asingle terminal.

INDUSTRIAL APPLICABILITY

As described above, the present invention makes it possible to monitorthe voltages of secondary cells accurately for the prevention ofoverdischarging and overcharging, and is thus very suitable for abattery pack employing lithium-ion cells, which pose a risk of smokingor the like when brought into an overdischarged or overcharged state.

What is claimed is:
 1. A power supply monitoring integrated circuitdevice for individually monitoring voltages of a plurality of cellsconnected in series to control charging or discharging operation of thecells, comprising: a plurality of pairs of input terminals provided onepair for each of the cells and each pair independently of the otherpairs for receiving the voltages of the cells, each pair of inputterminals including a first input terminal connected to a positive endof a particular cell and a second input terminal connected to a negativeend of that particular cell; a plurality of voltage dividing means fordividing the voltages of the cells received via the first and secondinput terminals; a plurality of comparators for comparing outputvoltages of the voltage dividing means with a predetermined voltage; aplurality of electric power input terminals for receiving electric powerfed through a resistor from a higher potential end of the cells tooperate the comparators individually; a control means connected to thecomparators so as to generate a stop signal for stopping the charging ordischarging operation when the voltage of at least one of the cellsexceeds the predetermined voltage; and an output terminal connected tothe control means for outputting the stop signal, wherein the electricpower input terminals include an electric power input terminal forreceiving electric power to be fed to the comparator corresponding tothe cell located at a positive side end of the cells and the secondinput terminals shared also for receiving electric power to be fed tothe comparators corresponding to the cells other than the cell locatedat the positive side end of the cells.
 2. A power supply monitoringintegrated circuit device as claimed in claim 1, wherein the cells arelithium-ion cells.
 3. A power supply monitoring integrated circuitdevice as claimed in claim 1, wherein two of the comparators areprovided for each of the cells, one comparator being used foroverdischarge detection, the other comparator being used for overchargedetection, the two comparators using different reference voltages forcomparison.
 4. A power supply monitoring integrated circuit device asclaimed in claim 3, wherein two of the voltage dividing means areprovided for each of the cells, one voltage dividing means beingconnected to corresponding one of the comparators for overdischargedetection, the other voltage dividing means being connected tocorresponding one of the comparators for overcharge detection.
 5. Apower supply monitoring integrated circuit device as claimed in claim 3,wherein each pair of the input terminals is connected to correspondingtwo of the comparators.
 6. A power supply monitoring integrated circuitdevice for individually monitoring voltages of a plurality of cellsconnected in series to control charging or discharging operation of thecells, comprising: a plurality of pairs of input terminals provided onepair for each of the cells for receiving the voltages of the cells, eachpair of input terminals including a first input terminal connected to apositive end of a particular cell and a second input terminal connectedto a negative end of that particular cell; a plurality of voltagedividing means for dividing the voltages of the cells received via thefirst and second input terminals; a plurality of comparators forcomparing output voltages of the voltage dividing means with apredetermined voltage; a plurality of electric power input terminals forreceiving electric power fed through a resistor from a higher potentialend of the cells to operate the comparators individually; a controlmeans connected to the comparators so as to generate a stop signal forstopping the charging or discharging operation when the voltage of atleast one of the cells exceeds the predetermined voltage; and an outputterminal connected to the control means for outputting the stop signal,wherein the electric power input terminals include an electric powerinput terminal for receiving electric power to be fed to the comparatorcorresponding to the cell located at a positive side end of the cellsand the second input terminals shared also for receiving electric powerto be fed to the comparators corresponding to the cells other than thecell located at the positive side end of the cells.